This page is intended to show the outline of the chip and to provide additional information that might not be clear from the data sheet.

 

The Xmega is a great new chip. It has a lot of hardware on board and a huge amount of hardware registers.

Some changes in the architecture are however dubious.(opinion of MCS)

 

The power of the AVR is/was the the linear memory architecture. In the Xmega this has been changed : the registers are placed into a separate address space. This makes code like this fail:

 

Clr r31

Ldi r30,10   ; point to register R10

Ld r24,z+   ; load value from R10 and inc pointer

 

Of course LDS/STS will not work to on the registers.

If your asm code contains such code you need to rewrite it.

 

Another change which has less impact is that when writing a word register, you need to start with the LSB first.

In non-Xmega you always had to write the MSB first.

 

 

There is no ISP programming support. Only JTAG and PDI is supported. Of course the MCS Bootloader can be used but you need to program the chip first.

 

 

There might be other changes. Despite these changes, the Xmega is great for new designs. It has up to 8 USARTS, internal oscillators, ADC, DAC, timers, multiple SPI and TWI.